Introduction to FPGA programming

Mirko Mariotti (Perugia University) and Andrea Triossi (Padova University)

Inglese

Prerequisites:

  • Basic notions of digital electronics (combinatorial and sequential circuits)
  • basic C++ programming with usage of templates
  • basic python programming
  • entry level knowledge of machine learning (not really needed, but it may help for the last part of the course)

Target skills and knowledge: The aim of the course is to provide a hands-on programming laboratory of Field-Programmable Gate Arrays (FPGA) through the VHDL hardware description language.

Course unit contents:

  • Introduction to FPGAs
  • FPGA Architecture
  • FPGA programming flow
  • VHDL language by examples: Introduction to the Vivado programming framework and the Arty A7 board, Combinational circuits on FPGA, Sequential circuits on FPGA, Arithmetic operations on FPGA
  • Case study: UART interface
  • High Level Synthesis (HLS): Programming flow, Number representations and arithmetic, Understanding and optimizing loops

2 ECTS, with 4 days of lectures (MON-THU) with 2 hours of lectures and 2 hours of exercises in the afternoon every day

15-19 June 2026

ISTRUZIONE DI QUALITÁ | IMPRESE, INNOVAZIONE E INFRASTRUTTURE | LOTTA CONTRO IL CAMBIAMENTO CLIMATICO

Introduction to FPGA programming

Mirko Mariotti (Perugia University) and Andrea Triossi (Padova University)

English

Prerequisites:

  • Basic notions of digital electronics (combinatorial and sequential circuits)
  • basic C++ programming with usage of templates
  • basic python programming
  • entry level knowledge of machine learning (not really needed, but it may help for the last part of the course)

Target skills and knowledge: The aim of the course is to provide a hands-on programming laboratory of Field-Programmable Gate Arrays (FPGA) through the VHDL hardware description language.

Course unit contents:

  • Introduction to FPGAs
  • FPGA Architecture
  • FPGA programming flow
  • VHDL language by examples: Introduction to the Vivado programming framework and the Arty A7 board, Combinational circuits on FPGA, Sequential circuits on FPGA, Arithmetic operations on FPGA
  • Case study: UART interface
  • High Level Synthesis (HLS): Programming flow, Number representations and arithmetic, Understanding and optimizing loops

2 ECTS, with 4 days of lectures (MON-THU) with 2 hours of lectures and 2 hours of exercises in the afternoon every day

15-19 June 2026

QUALITY EDUCATION | INDUSTRY, INNOVATION AND INFRASTRUCTURE | CLIMATE ACTION